Inverted Gate Vedic Multiplier in 90nm CMOS Technology

Chiranjit Rajendra Patel; Vivek Bettadapura Adishesha; Vivek Urankar; Keshav Vaidyanathan Bharadwaj

doi:doi:10.11648/j.ajece.20200401.12

| Peer-Reviewed

Inverted Gate Vedic Multiplier in 90nm CMOS Technology

Chiranjit Rajendra Patel, Vivek Bettadapura Adishesha, Vivek Urankar, Keshav Vaidyanathan Bharadwaj

Published in American Journal of Electrical and Computer Engineering (Volume 4, Issue 1)

Received: 16 June 2020 Accepted: 30 June 2020 Published: 7 July 2020

Views: Downloads:

Download PDF

Share This Article

Twitter
Linked In
Facebook

Abstract

This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.

Published in	American Journal of Electrical and Computer Engineering (Volume 4, Issue 1)
DOI	10.11648/j.ajece.20200401.12
Page(s)	10-15
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2020. Published by Science Publishing Group

Keywords

CMOS 90nm, Inverted Gate, Vedic Multiplier, Urdhva Tiryagbhayam, Carry Save Adder, Layout Design

References

[1]	Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja. Vedic mathematics: Sixteen simple Mathematical For- mulae from the Vedas. Delhi 1965.
[2]	Balraj Singh et al. “Analysis of CMOS based NAND and NOR Gates at 45 nm Technology”. International Journal of Electronics, Electrical and Computational System (IJEECS), Vol. 6 (Issue 4), April 2017.
[3]	Pawan Manoj Rathod et al. “Optimizing the Complex- ity of Matrix Multiplication Algorithm”. Interna- tional Journal of Engineering Research & Technology (IJERT), 5 (01), 2017.
[4]	MD. Belal Rashid et al. “VLSI Design and Implemen- tation of Binary Number Multiplier based on Urdhva Tiryagbhyam Sutra with reduced Delay and Area”. In- ternational Journal of Engineering Research and Tech- nology., 2013.
[5]	Harsha R et al. “Design of Vedic multiplier using Ur- dhva Tiryagbhyam Sutra”. International Journal of Advance Research, Ideas and Innovations in Technol- ogy, 5 (3), 2019.
[6]	Anuradha Singh and Neetu Gupta “Vedic mathematics For VLSI Design: A Review”. International Journal of Engineering Sciences & Research Technology, 2017.
[7]	Arish S and R. K. Sharma “An efficient binary mul- tiplier design for high speed applications using Karat- suba algorithm and Urdhva-Tiryagbhyam algorithm”. Global Conference on Communication Technologies (GCCT), pages 192–196, 2015.
[8]	N Janardan et al. “Implementation of 64 Bit Complex FloatingPoint Multiplier on FPGA using Vedic Math- ematics Sutra- Urdhva Tiryagbhyam”. International Journal of Innovative Technology and Exploring Engi- neering (IJITEE), 9 (04), 2020.
[9]	Chiranjit R Patel et al. “Vedic Multiplier in 45nm Tech- nology”. International Conference on Computing Methodologies and Communication (ICCMC), 2020.
[10]	Chandrashekara M N and Rohith S “Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder”. International Con- ference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), 2019.
[11]	Sandesh Sharma and Vangmayee Sharda “Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique”. International Journal of Engi- neering &Technology, 2018.
[12]	Manikannan G et al. “Low Power High Speed Full Adder Cell with XOR/XNOR Logic Gates in 90nmTechnology”. International Conference on Tech- nical Advancements in Computers and Communica- tions, 2017.
[13]	Akshata R et al. “Analysis of Vedic Multipliers”. Inter- national Conference on Computing, Communicationas and Energy Systems (ICCES), 2016.
[14]	Neil H E Weste and David Money Harris. CMOS VLSI Design: A circuits and systems perpespective, 4 edi- tion. Pearson.
[15]	Adel S Sedra and Kenneth C Smith. Microelectronics Circuits Theory and Applications.
[16]	Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. In Partha Bhat- tacharyya et al., editors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014.

Cite This Article

Plain Text BibTeX RIS

APA Style

Chiranjit Rajendra Patel, Vivek Bettadapura Adishesha, Vivek Urankar, Keshav Vaidyanathan Bharadwaj. (2020). Inverted Gate Vedic Multiplier in 90nm CMOS Technology. American Journal of Electrical and Computer Engineering, 4(1), 10-15. https://doi.org/10.11648/j.ajece.20200401.12

Copy | Download

ACS Style

Chiranjit Rajendra Patel; Vivek Bettadapura Adishesha; Vivek Urankar; Keshav Vaidyanathan Bharadwaj. Inverted Gate Vedic Multiplier in 90nm CMOS Technology. Am. J. Electr. Comput. Eng. 2020, 4(1), 10-15. doi: 10.11648/j.ajece.20200401.12

Copy | Download

AMA Style

Chiranjit Rajendra Patel, Vivek Bettadapura Adishesha, Vivek Urankar, Keshav Vaidyanathan Bharadwaj. Inverted Gate Vedic Multiplier in 90nm CMOS Technology. Am J Electr Comput Eng. 2020;4(1):10-15. doi: 10.11648/j.ajece.20200401.12

Copy | Download

@article{10.11648/j.ajece.20200401.12,
  author = {Chiranjit Rajendra Patel and Vivek Bettadapura Adishesha and Vivek Urankar and Keshav Vaidyanathan Bharadwaj},
  title = {Inverted Gate Vedic Multiplier in 90nm CMOS Technology},
  journal = {American Journal of Electrical and Computer Engineering},
  volume = {4},
  number = {1},
  pages = {10-15},
  doi = {10.11648/j.ajece.20200401.12},
  url = {https://doi.org/10.11648/j.ajece.20200401.12},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajece.20200401.12},
  abstract = {This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.},
 year = {2020}
}

Copy | Download

TY  - JOUR
T1  - Inverted Gate Vedic Multiplier in 90nm CMOS Technology
AU  - Chiranjit Rajendra Patel
AU  - Vivek Bettadapura Adishesha
AU  - Vivek Urankar
AU  - Keshav Vaidyanathan Bharadwaj
Y1  - 2020/07/07
PY  - 2020
N1  - https://doi.org/10.11648/j.ajece.20200401.12
DO  - 10.11648/j.ajece.20200401.12
T2  - American Journal of Electrical and Computer Engineering
JF  - American Journal of Electrical and Computer Engineering
JO  - American Journal of Electrical and Computer Engineering
SP  - 10
EP  - 15
PB  - Science Publishing Group
SN  - 2640-0502
UR  - https://doi.org/10.11648/j.ajece.20200401.12
AB  - This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.
VL  - 4
IS  - 1
ER  -

Copy | Download

Author Information

Chiranjit Rajendra Patel

Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Vivek Bettadapura Adishesha

Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Vivek Urankar

Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India
Keshav Vaidyanathan Bharadwaj

Electronics and Communication, RNS Institute of Technology, Bengaluru, Karnataka, India

Download PDF

Sections

Plain Text BibTeX RIS

APA Style

Chiranjit Rajendra Patel, Vivek Bettadapura Adishesha, Vivek Urankar, Keshav Vaidyanathan Bharadwaj. (2020). Inverted Gate Vedic Multiplier in 90nm CMOS Technology. American Journal of Electrical and Computer Engineering, 4(1), 10-15. https://doi.org/10.11648/j.ajece.20200401.12

Copy | Download

ACS Style

Chiranjit Rajendra Patel; Vivek Bettadapura Adishesha; Vivek Urankar; Keshav Vaidyanathan Bharadwaj. Inverted Gate Vedic Multiplier in 90nm CMOS Technology. Am. J. Electr. Comput. Eng. 2020, 4(1), 10-15. doi: 10.11648/j.ajece.20200401.12

Copy | Download

AMA Style

Chiranjit Rajendra Patel, Vivek Bettadapura Adishesha, Vivek Urankar, Keshav Vaidyanathan Bharadwaj. Inverted Gate Vedic Multiplier in 90nm CMOS Technology. Am J Electr Comput Eng. 2020;4(1):10-15. doi: 10.11648/j.ajece.20200401.12

Copy | Download

@article{10.11648/j.ajece.20200401.12,
  author = {Chiranjit Rajendra Patel and Vivek Bettadapura Adishesha and Vivek Urankar and Keshav Vaidyanathan Bharadwaj},
  title = {Inverted Gate Vedic Multiplier in 90nm CMOS Technology},
  journal = {American Journal of Electrical and Computer Engineering},
  volume = {4},
  number = {1},
  pages = {10-15},
  doi = {10.11648/j.ajece.20200401.12},
  url = {https://doi.org/10.11648/j.ajece.20200401.12},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajece.20200401.12},
  abstract = {This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.},
 year = {2020}
}

Copy | Download

TY  - JOUR
T1  - Inverted Gate Vedic Multiplier in 90nm CMOS Technology
AU  - Chiranjit Rajendra Patel
AU  - Vivek Bettadapura Adishesha
AU  - Vivek Urankar
AU  - Keshav Vaidyanathan Bharadwaj
Y1  - 2020/07/07
PY  - 2020
N1  - https://doi.org/10.11648/j.ajece.20200401.12
DO  - 10.11648/j.ajece.20200401.12
T2  - American Journal of Electrical and Computer Engineering
JF  - American Journal of Electrical and Computer Engineering
JO  - American Journal of Electrical and Computer Engineering
SP  - 10
EP  - 15
PB  - Science Publishing Group
SN  - 2640-0502
UR  - https://doi.org/10.11648/j.ajece.20200401.12
AB  - This paper proposes the design and implementation of an enhanced binary multiplication technique. Vedic Mathematics is a system of mathematics that was discovered by Indian mathematician Jagadguru Shri Bharathi Krishna Tirthalji in the period between 1911 and 1918. The main objective of this paper is to design an improved binary multiplier which is faster and low-powered. The performance of our proposed full adder design is proven to be more effective in comparison with the standard full adder cell both designed in 90nm. The proposed modified 2-Bit and 4-Bit Vedic multipliers also beat the existing Vedic multiplier based in Urdhva Tiryagbhyam sutra in terms of operating frequency, energy and area. ThedesignsareimplementedoncadenceVirtuoso90nmCMOStechnology operating at 2V supply. Comparedtotheexisting standard fulladderdesigns in 90nm, the proposed implementation has shown that it offers significant improvements in terms of power and speed consuming 60% less power and is able to operate 20% faster. The proposed 2-Bit multiplier operated at 2V is proven to be more effective. The design was further extended to realise a 4-Bit multiplier. The power consumed by the standard 4- Bit multiplier designed using standard 90nm cells was 361.2µW and the power consumed by the proposed 4-Bit multiplier design was found to be 290.2µW, which reflectsa 20% decrease in the power usage.
VL  - 4
IS  - 1
ER  -

Copy | Download