An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]

Mahesh Kumar

doi:doi:10.11648/j.ajece.20190301.15

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An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]

Mahesh Kumar

Published in American Journal of Electrical and Computer Engineering (Volume 3, Issue 1)

Received: 29 November 2018 Accepted: 5 January 2019 Published: 2 July 2019

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Abstract

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

Published in	American Journal of Electrical and Computer Engineering (Volume 3, Issue 1)
DOI	10.11648/j.ajece.20190301.15
Page(s)	38-45
Creative Commons	This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.
Copyright	Copyright © The Author(s), 2019. Published by Science Publishing Group

Keywords

Fault Diagnosis, Built-in Self-Test (BIST), Configurable Logic Block (CLB), Field-Programmable Gate Array (FPGA), Testing

References

[1]	Xilinx Inc., San Jose, CA, “Xilinx EasyPath Solutions,” 2006. [Online]. Available: www.xilinx.com.
[2]	W. -J. Huang and E. J. McCluskey, “Column-based precompiled configuration techniques for FPGA fault tolerance,” in Proc. IEEE Symp. Field-Program. Custom Comput. Mach., 2001, pp. 137–146.
[3]	C. T. Huang, J. -R. Huang, C. -F. Wu, C. -W. Wu, and T. -Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Des. Test Comput., vol. 16, no. 1, pp. 59–70, Jan.–Mar. 1999.
[4]	L. -T. Wang, C. -W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures. San Francisco, CA: Elsevier (Morgan Kaufmann), 2006.
[5]	R. P. Treuer and V. K. Agarwal, “Built-in self-diagnosis for repairable embedded RAMs,” IEEE Des. Test Comput., vol. 10, no. 2, pp. 24–33, Jun. 1993.
[6]	C. -W. Wang, C. -F. Wu, J. -F. Li, C. -W. Wu, T. Teng, K. Chiu, and H. -P. Lin, “A built-in self-test and self-diagnosis scheme for embedded SRAM,” J. Electron. Test.: Theory Appl., vol. 18, no. 6, pp. 637–647, Dec. 2002.
[7]	J. Vollrath, U. Lederer, and T. Hladschik, “Compressed bit fail maps for memory fail pattern classification,” in Proc. IEEE Euro. TestWorkshop (ETW), 2000, pp. 125–130.
[8]	V. N. Yarmolik, S. Hellebrand, and H. Wunderlich, “Self-adjusting output data compression: An efficient BIST technique for RAMs,” in Proc. Conf. Des., Autom., Test Euro. (DATE), 1998, pp. 173–179.
[9]	S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N.Yarmolik, “Error detecting refreshment for embedded DRAMs,” in Proc. IEEE VLSI Test Symp. (VTS), 1999, pp. 384–390.
[10]	S. Hellebrand, H. Wunderlich, A. Ivaniuk, Y. Klimets, and V. N.Yarmolik, “Efficient online and offline testing of embedded DRAMs,” IEEE Trans. Comput., vol. 51, no. 7, pp. 801–809, Jul. 2002.
[11]	A. K. Sharma, Semiconductor Memories: Technology, Testing and Reliability. New York: Wiley, 2002.
[12]	Y. -H. Lee, Y. -G. Jan, J. -J. Shen, S. -W. Tzeng, M. -H. Chuang, and J. -Y. Lin, “A DFT architecture for a dynamic fault model of the embedded mask ROM of SoC,” in Proc. Int. Workshop Memory Technol. Design Testing, 2005, pp. 78–82.
[13]	T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int. Test Conf. (ITC), 2000, pp. 567–574.
[14]	S. R. Patil, D. B. Musle, “Implementation of BIST technology for fault detection and repair of the multiported memory using FPGA”, International conference of Electronics, Communication and Aerospace Technology (ICECA), December 2017.
[15]	M. B. Tahoori, “Diagnosis of open defects in FPGA interconnects,” in Proc. IEEE Int. Conf. Field-Program. Technol., 2002, pp. 328–331.
[16]	M. B. Tahoori, “Application dependent testing of FPGAs,” IEEE Trans. Very Large Scale Integr. (VLSI) Circuits, vol. 14, no. 9, pp. 1024–1033, Sep. 2006.
[17]	M. Abramovici and C. Stroud, “BIST-based detection and diagnosis of multiple faults in FPGAs,” in Proc. Int. Test Conf., 2000, pp. 785–794.
[18]	A. Doumar and H. Ito, “Detecting, diagnosing, and tolerating faults in SRAM-Based field programmable gate arrays, a survey,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 3, pp. 386–405, Mar. 2003.
[19]	W. Quddus, A. Jas, and N. A. Touba, “Configuration self-test in FPGA based reconfigurable systems,” in Proc. ISCAS, 1999, pp. 97–100.
[20]	C. Stroud, E. Lee, and M. Abramovici, “BIST based diagnostics of FPGA logic blocks,” in Proc. Int. Test Conf, 1997, pp. 539–547.
[21]	C. Stroud, S. Konala, C. Ping, and M. Abramovici, “Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: Bist without overhead!),” in Proc. VLSI Test Symp., 1996, pp. 387–392.
[22]	J. T. Chen, J. Khare, K. Walker, S. Shaikh, J. Rajski, and W. Maly, “Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring,” in Proc. Int. Test Conf. (ITC), 2001, pp. 258–267.
[23]	Anita Aghaie, Mehran Mozaffari Kermani, Reza Azarderakhsh, “Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 37, Issue 4, April 2018, pp 901 – 905.
[24]	Gehad I. Alkady, Nahla A. El-Araby, M. B. Abdelhalim, H. H. Amer, A. H. Madian, “A fault-tolerant technique to detect and recover from open faults in FPGA interconnects”, in the proceedings of 14th Biennial Baltic Electronic Conference (BEC), November 2015.

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Mahesh Kumar. (2019). An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. American Journal of Electrical and Computer Engineering, 3(1), 38-45. https://doi.org/10.11648/j.ajece.20190301.15

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ACS Style

Mahesh Kumar. An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. Am. J. Electr. Comput. Eng. 2019, 3(1), 38-45. doi: 10.11648/j.ajece.20190301.15

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AMA Style

Mahesh Kumar. An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. Am J Electr Comput Eng. 2019;3(1):38-45. doi: 10.11648/j.ajece.20190301.15

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@article{10.11648/j.ajece.20190301.15,
  author = {Mahesh Kumar},
  title = {An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]},
  journal = {American Journal of Electrical and Computer Engineering},
  volume = {3},
  number = {1},
  pages = {38-45},
  doi = {10.11648/j.ajece.20190301.15},
  url = {https://doi.org/10.11648/j.ajece.20190301.15},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajece.20190301.15},
  abstract = {In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.},
 year = {2019}
}

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TY  - JOUR
T1  - An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]
AU  - Mahesh Kumar
Y1  - 2019/07/02
PY  - 2019
N1  - https://doi.org/10.11648/j.ajece.20190301.15
DO  - 10.11648/j.ajece.20190301.15
T2  - American Journal of Electrical and Computer Engineering
JF  - American Journal of Electrical and Computer Engineering
JO  - American Journal of Electrical and Computer Engineering
SP  - 38
EP  - 45
PB  - Science Publishing Group
SN  - 2640-0502
UR  - https://doi.org/10.11648/j.ajece.20190301.15
AB  - In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.
VL  - 3
IS  - 1
ER  -

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Author Information

Mahesh Kumar

Department of Electronics, PSG College of Arts & Science, Coimbatore, India

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APA Style

Mahesh Kumar. (2019). An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. American Journal of Electrical and Computer Engineering, 3(1), 38-45. https://doi.org/10.11648/j.ajece.20190301.15

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ACS Style

Mahesh Kumar. An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. Am. J. Electr. Comput. Eng. 2019, 3(1), 38-45. doi: 10.11648/j.ajece.20190301.15

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AMA Style

Mahesh Kumar. An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]. Am J Electr Comput Eng. 2019;3(1):38-45. doi: 10.11648/j.ajece.20190301.15

Copy | Download

@article{10.11648/j.ajece.20190301.15,
  author = {Mahesh Kumar},
  title = {An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]},
  journal = {American Journal of Electrical and Computer Engineering},
  volume = {3},
  number = {1},
  pages = {38-45},
  doi = {10.11648/j.ajece.20190301.15},
  url = {https://doi.org/10.11648/j.ajece.20190301.15},
  eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.ajece.20190301.15},
  abstract = {In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.},
 year = {2019}
}

Copy | Download

TY  - JOUR
T1  - An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST]
AU  - Mahesh Kumar
Y1  - 2019/07/02
PY  - 2019
N1  - https://doi.org/10.11648/j.ajece.20190301.15
DO  - 10.11648/j.ajece.20190301.15
T2  - American Journal of Electrical and Computer Engineering
JF  - American Journal of Electrical and Computer Engineering
JO  - American Journal of Electrical and Computer Engineering
SP  - 38
EP  - 45
PB  - Science Publishing Group
SN  - 2640-0502
UR  - https://doi.org/10.11648/j.ajece.20190301.15
AB  - In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.
VL  - 3
IS  - 1
ER  -

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